Capturing and evaluating high speed data streams

Details Capturing and evaluating high speed data streams Capturing and evaluating high speed data streams

2000-08-09

2004-02-17

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S819000

Reexamination Certificate

active

06694462

ABSTRACT:

BACKGROUND OF THE INVENTION
Manufacturers of integrated circuits use automatic test equipment (ATE) to verify newly manufactured devices. ATE allows manufacturers to diagnose device faults early in the manufacturing process, and thus allows manufacturers to save costs. ATE also allows manufacturers to grade devices across different levels of performance. As manufacturers generally receive higher prices for better-performing chips, the ability to accurately test integrated circuits translates into increased profits.
A primary goal of automatic test equipment (ATE) is to test electronic devices quickly and accurately. As devices become faster and more complex, ATE must advance to keep pace with these changes.
The popularity of Serializer/Deserializer transceivers, commonly called “SerDes” devices, has increased with recent growth in the telecommunications and networking industries. SerDes devices convert parallel bit streams into serial bit streams that change at a multiple of the input, parallel data rate. They also perform the reverse function of deserializing serial bit streams, by converting them into parallel bit streams that change at a fraction of the serial data rates. SerDes devices are now available at serial data rates up to 2.5 GB/s (billion bits per second), and 10 GB/s parts will soon be available.
FIG. 1
is a highly simplified illustration of a conventional component tester
100
. The component tester
100
includes a host computer
110
, a timing generator
112
, a memory
114
, and a system clock
116
. The host computer
110
stores a test program (not shown) for controlling the resources of the component tester
100
. In response to the system clock
116
, the timing generator
112
produces timing signals
118
at precise instants in time defined by the test program. The timing signals
118
control a plurality of driver circuits, shown generally as driver circuits
120
a
-
120
x
, and a plurality of detector circuits, shown generally as detector circuits
122
a
-
122
x.
The test program specifies data representative of digital states to which the driver circuits
120
are to be driven. These data are conventionally known as “drive data.” The test program also specifies data representative of values expected from the DUT in response to the drive data, i.e., “expect data.” The test system
100
stores the drive data in the memory
114
, and sequentially applies the drive data to the driver circuits
120
at precise instants in time. In response, the driver circuits
120
generate electrical signals. The electrical signals are applied to inputs of a DUT (device under test)
124
, and the DUT
124
generates outputs in response to its inputs. As the test system
100
applies input signals to the DUT
124
, it simultaneously causes the detector circuits
122
to strobe output signals from the DUT. Data representative of signals captured by the detector circuits are stored in the memory
114
. To determine whether a device passes or fails, the test program compares the captured data from the detector circuits
122
with the expect data. If the actual data matches the expect data, the test program generally passes. Otherwise, the test program generally fails.
State-of-the-art component testers can generate digital waveforms at speeds up to several hundred megahertz. This still falls short of the 10 GB/s needed to directly test the fastest currently available SerDes devices at full speed.
Previous attempts at measuring high-speed serial data streams with component testers have made use of specialized instruments called TJD's (Time Jitter Digitizers). TJD's detect events at their inputs—for example, electrical signals changing state—and apply time-stamp values indicative of the times at which the detected events occur. For testing serial data streams, a TJD captures the serial data stream. A tester then reads back events and corresponding time-stamp values to accurately report the timing of edges embedded within the serial data stream. Because they are complex, multifunctional instruments, TJD's tend to be expensive. They also tend to operate at speeds that are slower than those required for testing the fastest SerDes devices.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to measure the timing characteristics of high-speed serial data streams.
It is a further object of the invention to readily integrate with conventional automatic test equipment.
To achieve the foregoing objects and other objectives and advantages, a conventional test system is provided with a latching comparator to facilitate the testing of a device under test (DUT). The latching comparator has a Latch Enable input, which, when activated, causes the latching comparator to hold at its output the binary state of its input at the instant of activation. Driver circuits from the tester are coupled to inputs of the DUT, and the output of the DUT is coupled to the input of the latching comparator. Under control of a test program, the tester applies a test pattern to the inputs of the DUT. The DUT in turn generates an output signal. At a precisely controlled instant in time relative to the DUT output signal, the tester activates the Latch Enable input and samples the output of the latching comparator. The tester repetitively applies the test pattern and activates the Latch Enable input, to acquire a plurality of samples of the DUT output signal at the controlled instant in time relative to the DUT output signal.
The timing for activating the Latch Enable input is then changed to correspond to a different location relative to the DUT output signal, and a plurality of samples of the DUT output signal are acquired at the new location. This process of sampling the DUT output signal and changing the timing for activating the Latch Enable input is repeated until a plurality of samples are collected for all desired locations of the DUT output signal.
Using the stored samples, the tester computes a separate average—or probability—of samples acquired for each location relative to the DUT output signal. The averages are then sequenced as a function of time, and the results are analyzed.


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patent: 4354177 (1982-10-01), Sloane
patent: 5737342 (1998-04-01), Ziperovich
patent: 6260166 (2001-07-01), Bhavsar et al.
patent: 6324224 (2001-11-01), Ikeda
patent: 6331999 (2001-12-01), Ducaroir et al.
patent: 6536005 (2003-03-01), Augarten
patent: 0518116 (1992-12-01), None
patent: WO 99/51941 (1999-10-01), None
A CMOS high-speed data recovery circuit using the matched delay sampling technique Jin-Ku Kang; Wentai Liu; Cavin, R.K., I IEEE Journal of Solid-State Circuits, vol.: 32 Issue: 10, Oct. 1997 Page(s): 1588-1596.*
Alan J. Reiss, Edge Find 1999, Apr. 12, 1999, Teradyne, Inc.
Time Jitter Digitizer, Version 6.4, Jun., 1999, Teradyne, Inc.
“Statistical Analysis with Messy Data” Gordon B. Saksena, Teradyne, Inc., Mar. 28, 2000.
“Optimizing Edgefinds” Gordon B. Saksena, Teradyne, Inc., 1998.

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