Built-in-self-test circuit for RAMBUS direct RDRAM

Details Built-in-self-test circuit for RAMBUS direct RDRAM Built-in-self-test circuit for RAMBUS direct RDRAM

1999-04-30

2003-11-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S736000

Reexamination Certificate

active

06647524

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the built-in-self-test (BIST) of dynamic random access memory (DRAM), and more particularly, to a BIST circuit for RAMBUS DRAM.
BACKGROUND OF THE INVENTION
One objective of built-in self-test (BIST) for random access memory is to translate a test algorithm into a sequence of commands, data, and addresses to be applied to the memory under test. In the prior art, a variety of techniques have been utilized to provide BIST for RAM. Traditionally, a hard-wired finite state machine is used to implement the translation process. To provide the capability of at-speed testing, the BIST circuit operates as fast as the memory under test. A disadvantage of the approach is that the finite state machine is tailored into a specific set of test patterns whose complexity depends on the test algorithm. As the complexity of the test algorithm increases, this approach may be inadequate because the finite state machine may become too large and too slow to produce a test pattern in each clock cycle to intensively exercise the memory under test.
Other BIST circuits, known to be programmable or configurable, provide certain flexibility by configuration variables that determine specific test patterns and sequences to be applied to the memory array. For example, U.S. Pat. No. 5,173,906 entitled “Built-in Self Test for Integrated Circuits” (issued Dec. 22, 1992 to Dreibelbis et al.) discloses a circuit that provides both fixed and programmable test patterns for a RAM array. U.S. Pat. No. 5,224,101 entitled “Micro-Coded Self-Test Apparatus for a Memory Array” (issued Jun. 29, 1993 to Popyack, Jr.) discloses a circuit that uses a micro-coded sequence defined in the contents of a read-only memory to produce the test patterns.
U.S. Pat. No. 5,301,156 entitled “Configurable Self-Test for Embedded RAMS” (issued Apr. 5, 1994, to Talley) discloses a circuit that has a serial path that passes through the address, command, and data portions of the circuit to shift in a test or control pattern and to shift out the results, each scan requiring several clock cycles.
However, a need still exists for a BIST circuit specifically adapted for a RAMBUS DRAM memory.
SUMMARY OF THE INVENTION
A built-in-self-test (BIST) circuit for RAMBUS DRAM is disclosed. Unlike other conventional memory devices, a RAMBUS DRAM operates at a much higher speed (e.g., 400 MHz) with a complicated protocol imposed on its input stimuli. In order to provide at-speed testing, a new BIST architecture is needed. The new architecture consists of three major components—two interacting finite state machines (FSMs) and a high-speed time-division multiplexer. The two finite state machines, defining the underlying test algorithms jointly, are used to generate a sequence of generic memory commands. Through the time-division multiplexer, each memory command is then further mapped into a multi-cycle packet compliant to the specification of a target RAMBUS DRAM. Among these components, the finite state machines often form the performance bottleneck. We therefore use a simple master-slave synchronization mechanism to convert these two finite state machines into a multi-cycle path component, thereby eliminating the timing criticality.


REFERENCES:
patent: 5655113 (1997-08-01), Leung et al.
patent: 5729152 (1998-03-01), Leung et al.
patent: 5748557 (1998-05-01), Kang
patent: 5818772 (1998-10-01), Kuge
patent: 5844438 (1998-12-01), Lee
patent: 6182253 (2001-01-01), Lawrence et al.
patent: 6272577 (2001-08-01), Leung et al.

Affiliated with

Also associated with

Rating

Built-in-self-test circuit for RAMBUS direct RDRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Built-in-self-test circuit for RAMBUS direct RDRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Built-in-self-test circuit for RAMBUS direct RDRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3125672