Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-13
2004-01-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000, C714S733000, C714S738000, C714S734000
Reexamination Certificate
active
06684357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip test, and more particularly to an apparatus and method of testing a video decoder in a system level.
2. Description of the Related Art
Generally, the fabrication of an application specific integrated circuit (ASIC) chip includes a chip testing process. This testing process is briefly divided into a process of checking whether the chip logic is correctly implemented, and a process of checking whether the actual chip function is correctly implemented.
Such a chip test is for confirming whether or not a correct output pattern comes out with respect to a determined input pattern. At this time, since the quantity and the scale of the input pattern are closely related to the unit cost of the chip, the testing process is performed for the minimum amount of the input pattern.
Accordingly, due to the limitation of the amount of pattern to be tested, the fault of the chip may not be sometimes found.
In the event that a system is constructed using the ASIC chip fabricated without finding out the fault thereof in the above-described testing process, the system may malfunction, and it is difficult to grasp which IC contains the fault if an error occurs in the system due to the fault of the chip.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a chip testing apparatus and method that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a chip testing apparatus and method which can confirm in the system level whether or not any fault exists in the chip itself overlooked in the process of fabricating the ASIC chip.
Another object of the present invention is to provide a chip testing apparatus and method which can confirm the error occurring in the system board using the judgement result of the chip fault in the system level.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the chip testing apparatus in a system constructed using at least one chip, includes a testing section, provided in the corresponding chip, for judging a normal/abnormal state of the corresponding chip by obtaining a test signature by accumulating a bit stream inputted in a system level using a predetermined testing method, and by comparing the obtained test signature with a reference signature previously obtained and stored.
In another aspect of the present invention, there is provided a video decoder comprising a video decoding section for receiving and decoding a video bit stream to be tested in a system level, and a testing section for discriminating a normal/abnormal state of the video decoding section by obtaining a test signature by accumulating video-decoded pixel values using a predetermined testing method, and by comparing the obtained test signature with a reference signature previously obtained and stored.
According to the present invention, the testing section obtains the test signature by accumulating the input bit stream through a check-summing process using a simple adder.
According to the present invention, the testing section obtains the test signature by accumulating the input bit stream by a multiple input shift register (MISR) using a shift register.
According to the present invention, the testing section comprises a test control section for controlling a testing operation by determining a test mode in accordance with an input test method, test unit, and bit width, an operation section for outputting the test signature by accumulating the pixel values decoded and inputted in accordance with the test mode determined by the test control section, a comparator for comparing the test signature outputted from the operation section with a pre-stored reference signature under the control of the test control section to output a result of comparison, and a host control section for obtaining and storing the reference signature to be used for the test, outputting to the test control section the test method, test unit, and bit width at that time, and judging whether the corresponding chip is in the normal or abnormal state in accordance with the comparison result of the comparator to enable a tester to recognize a result of judgement.
According to the present invention, the test unit used for the accumulation is the unit of a picture or of a sequence.
In still another aspect of the present invention, there is provided a chip testing method in a system constructed using at least one chip, comprising the steps of receiving and decoding a video bit stream to be tested in a system level, and discriminating whether the corresponding chip is in a normal or abnormal state by obtaining a test signature by accumulating video-decoded pixel values using a predetermined testing method, and by comparing the obtained test signature with a reference signature previously obtained and stored.
According to the present invention, the step of discriminating the normal/abnormal state of the chip obtains the test value by selecting one of a check-summing process using a simple adder and a multiple input shift register (MISR) process using a shift register as the testing method, and accumulating the pixel values outputted at the video decoding step accordingly.
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Birch & Stewart Kolasch & Birch, LLP
De'cady Albert
Gandhi Dipakkumar
LG Electronics Inc.
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