Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-07-02
2001-02-06
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06185712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to Dynamic Random Access Memories (DRAMs) and, more particularly to DRAMs with Built In Self Test (BIST) Capability.
2. Background Description
State of the art Dynamic Random Access Memories (DRAM) and logic chips, such as microprocessors, may include Built In Self Test (BIST) capability. The BIST logic tests the DRAM or logic according to predefined tests to uncover any defective array elements.
Such a state of the art logic and DRAM is designed to function at what are defined to be worst case conditions. Normally, such a conservative worst case design includes some design margin to assure functionality that limits the microprocessor's or DRAM's actual performance to something less than the its full capability. Design margin verses performance is a trade off that designers must make at design to maximize chip manufacturing yield and guarantee chip functionality to specification.
Consequently, even though such a chip may include individual circuits capable of higher performance, its performance restricted by its slowest circuits. Further, even though some circuits might be selectively tuned in place, for an overall chip performance improvement, all circuits are set for the slowest circuits.
Thus, there is a need for integrated circuit chips wherein individual circuits may be tuned for optimum performance.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to improve integrated circuit chip performance.
It is another purpose of the present invention to improve DRAM performance and yield.
The present invention is an integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.
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Kirihata Toshiaki
Wait Christopher Douglas
Abate Joseph P.
Chung Phung M.
International Business Machines - Corporation
McGuireWoods LLP
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