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Test interface for random access memory (RAM) built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test interface, system, and method for testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test language conversion method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test limits based on position

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and apparatus using energy consumption ratio

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and architecture for circuits having inputs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and test circuit for electronic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method for a semiconductor integrated circuit having a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method for high speed semiconductor devices using a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method of chips in a semiconductor wafer employing a test a

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test method of semiconductor intergrated circuit and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test methodology based on multiple skewed scan clocks

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode circuit capable of surely resetting test mode signals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode control circuit and method for using the same in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode features for synchronous pipelined memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test mode for pin-limited devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode setup circuit for microcontroller unit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode soft reset circuitry and methods

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test output compaction for responses with unknown values

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test output compaction using response shaper

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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