Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-18
2003-01-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S819000
Reexamination Certificate
active
06513137
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of testing of integrated circuits. More specifically, the invention relates the testing of integrated logic circuits to detect redundant faults that are not observable on the logic static outputs of the circuits.
BACKGROUND
Traditional test methods often detect the presence of faulty electronic circuits by observing the response of circuit output logic values to various inputs. Such traditional methods do not always provide adequate identification of circuits in which defects exist, particularly where the defects are located at points in the circuit where the output signals do not reveal the existence of these defects, for example, redundant faults.
In order to address the problems noted with the output logic based test methods, delay test methods were developed to measure the speed of the output response. Unfortunately delay test methods also do not detect faults that are logically redundant.
Dynamic test methods also exploit circuit delays to detect faults, including some that are redundant. However these test techniques are dependent on possessing accurate delay models for the circuit being tested so that implementation of the tests is arduous and expensive.
Another collection of test techniques has been developed for testing circuits by the measurement of the supply current consumed by the circuits. A variety of these tests are known as I
ddt
test methods.
One variant of the I
ddt
approach involves the application of pulses to the supply rails and measurement of the transient response of the circuit.
A second variant of the I
ddt
approach is to measure the current drawn by either individual gates or by small collections of gates that make up the electronic circuit.
A third approach is to measure the supply current transients for the entire circuit in response to input changes.
The methods used to monitor the supply current transients may also be varied. The direct approach is to measure each individual transient, perhaps combined with spectral analysis. Another approach is to measure the average current over several transitions.
Each test approach has its own advantages. Methods which measure current consumption for small groups of gates, rather than the entire circuit, provide more information, but are more expensive than conventional output logic based testing. Individual transient measurements may provide more information than average currents but they are harder to measure, especially in high speed circuits.
All of these test measurements are affected by process variations between otherwise acceptable circuits as they are manufactured. Because of the process variations, the currents consumed by a perfect fault-free circuit may vary substantially. In general, it can be shown that the percentage impact of process variations is greater for individual transients measured for small collections of gates than for average currents measured for large collections of gates.
Therefore, a need exists for a method and apparatus that allows for an identification of flawed circuits containing combinationally redundant faults, without being subject to impact of process variations in the manufacturing of the electronic circuits.
SUMMARY
Those skilled in the art, upon reading and understanding the present specification, will appreciate that the present test technique satisfies the aforementioned needs in the art and several other needs not expressly mentioned herein. A method and apparatus for testing an electronic circuit is provided. This method includes connecting the circuit to a power supply, applying input vectors V
1
and V
2
as inputs to the circuit repeatedly in alternation at a frequency f, and measuring the average energy consumed by the circuit in undergoing repetitive transitions from a first input vector to a second input vector. It also provides for calculating the energy consumption ratio of the measured energy consumed on the energy test by the circuit being tested to the energy consumed on the benchmark transition by the same circuit and identifying the circuit being tested as faulty where its energy consumption ratio differs from that of good circuits by more than the amount that the ratio could be expected to differ by process variations in the manufacturing process.
In one application, the method of measuring the energy consumed is performed by measuring the average power supply current while the supply voltage is held constant. In another application, an energy test pair of input vectors V
1
and V
2
are generated so that the percentage transition difference between the good and faulty circuits is maximized as the pair of input vectors is alternated.
In one embodiment the method of selecting an energy test set E
t
of input vectors V
1
and V
2
for practicing the method of claim
3
in connection with a fault on line z involves applying a plurality of first test vectors, determining for each test vector the number of transitions N
D
that occur differently in the good and faulty circuits, selecting the first test vector which maximizes N
D
and designating it as D
max
, applying a plurality of second test vectors in alternation with D
max
and the signal at line z alternates in response to the application of the alternating inputs, selecting one of the second test vectors which minimizes the number of transitions that are common to the good and faulty circuits and designating that test vector as S
v
and comparing the inputs in D
max
and S
v
to each other and generating energy test vector E
t
by setting all inputs which have the same value k in both D
max
and S
v
to k in E
t
, setting all inputs which have the value 1(0) in D
max
and (0)1 in S
v
to T({overscore (T)}) in E
t
, setting all inputs which are specified to be a value of k in only one of D
max
or S
v
to k in E
t
, setting all inputs unspecified in both D
max
and S
v
to 0 and simulating the circuit logic and computing the values of the internal signals using the simulated circuit logic.
This summary is intended to be a general overview of the present test technique and is not intended in a limiting or exclusive sense. The invention described in the detailed description has a scope provided by the attached claims and their equivalents.
REFERENCES:
patent: 5029171 (1991-07-01), Lee et al.
patent: 5377201 (1994-12-01), Chakradhar et al.
patent: 5586125 (1996-12-01), Warner
patent: 5642362 (1997-06-01), Savir
patent: 5657240 (1997-08-01), Chakradhar et al.
patent: 5815416 (1998-09-01), Liebmann et al.
patent: 6169960 (2001-01-01), Ehrichs
patent: 6237117 (2001-05-01), Krishnamoorthy
patent: 07248360 (1995-09-01), None
Vinnakota, B.; Monitoring power dissipation for fault detection; Proceedings of 14th VLSI Test Symposium, 1996, Pp.: 483-488.
Cortner J. Max
Jiang Wanli
Vinnakota Bapiraju
Cardiac Pacemakers Inc.
De'cady Albert
Schwegman Lundberg Woessner & Kluth P.A.
Torres Joseph D.
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