Test mode soft reset circuitry and methods

Details Test mode soft reset circuitry and methods Test mode soft reset circuitry and methods

2011-06-14

2011-06-14

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S023000

Reexamination Certificate

active

07962819

ABSTRACT:
An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.

REFERENCES:
patent: 5784625 (1998-07-01), Walker
patent: 6418545 (2002-07-01), Adusumilli
patent: 7249298 (2007-07-01), Sim
patent: 2006/0279439 (2006-12-01), Swoboda

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