Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-07-22
2008-08-26
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
07418639
ABSTRACT:
A test interface is configured to connect to a testing device and a communications device. The communications device may be configured to receive a data signal (that includes a desired data portion) from the test machine. The interface may include a data capture device and a buffer. The data capture device may be configured to receive a framing pulse signal from the communications device, to receive a framing pulse enable signal from the testing device, and to generate a reset signal in response to receiving the framing pulse signal and the framing pulse enable signal. The buffer may be configured to store the data signal from the communications device, and to clear all stored data in the buffer and store the desired data portion in response to receiving the reset signal.
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Fish & Richardson P.C.
Intel Corporation
Louis-Jacques Jacques
Tabone, Jr. John J.
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