Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-15
2009-02-10
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S719000, C714S738000
Reexamination Certificate
active
07490279
ABSTRACT:
Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algorithms and techniques have been proposed for testing random access memory (RAM) devices. The present invention provides an architecture for the memory-test interface that allows the serial transfer of the test background data from the BIST controller to the interface of the memory-under-test using a single bit with serial-to-parallel data conversion using a shift register in the memory interface. The size of the shift register is equal to the word width of the memory-under-test.
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patent: 2005/0210352 (2005-09-01), Ricchetti et al.
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B. Nadeau-Dostie et al., “A Serial Interfacing Technique for Built-In and External Testing of Embedded Memories,”IEEE 1989 Custom Integrated Circuits Conference, vol. CH2671-6 (1989), pp. 22.2.1-22.2.5.
Kumar Rahul
Maturi Suryanarayana R.
Ray Partha
National Semiconductor Corporation
Stallman & Pollock LLP
Ton David
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