Test mode for pin-limited devices

Details Test mode for pin-limited devices Test mode for pin-limited devices

2006-04-06

2008-08-19

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07415647

ABSTRACT:
A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control the internal circuitry of the device). Accordingly, the pin-limited IC device continues to operate within specifications while the predetermined signal pattern is transmitted on the selected power supply pin or pins. A test mode circuit generates a switch control signal in response to the predetermined signal pattern to connect an output pin of the device, for example, to an internal node of the device. The pattern recognition circuit sets a latch when the predetermined signal pattern is detected, and the latch is reset when the device is powered down then powered up.

REFERENCES:
patent: 5414861 (1995-05-01), Horning
patent: 5965997 (1999-10-01), Alwardi et al.
patent: 7026855 (2006-04-01), Sueoka et al.
patent: 2006/0132111 (2006-06-01), Jacobs et al.

Affiliated with

Also associated with

Rating

Test mode for pin-limited devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test mode for pin-limited devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test mode for pin-limited devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4004003