Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-20
2001-03-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06199185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to speed tests of semiconductor integrated circuit devices. More particularly, the present invention is directed to a method for testing high speed semiconductor memory with a tester having a maximum frequency lower than the operational memory speed by using a clock modulation technique.
2. Description of the Related Arts
A large percentage of conventional Dynamic Random Access Memory (DRAM) devices have been sold with a fast page mode function, and are termed Fast-Page Mode DRAMs. These devices were generally incorporated in x486 and older PENTIUM based microprocessors. A fast page mode operation in a DRAM allows faster data operations within a page boundary defined by a row address. In general, this is accomplished by holding the row address strobe (RAS) signal at an active, low voltage level while toggling the column address strobe (CAS) signals to execute faster memory cycles. Typically, selecting a new row takes about three times longer than selecting another column in the same row. In the CAS signal, a high voltage level is the inactive state and is used to indicate that a change in column address will follow. When the memory is being accessed at two different columns on the same row (i.e., the same page), a mode of operation called the page-page mode, the CAS must remain at the inactive high level for a duration called the CAS precharge time, tcp, for a given memory device to properly recognize that a change of column address is occurring. The minimum CAS precharge time, i.e., minimum t
CP
, is a parameter that varies among different memory devices.
Another enhanced performance option for a DRAM is known as an extended data out (EDO)—sometimes referred to as hyper page mode. A DRAM that includes this feature is termed an EDO DRAM. The EDO DRAM is similar in fashion to the Fast-Page Mode DRAM but operates at an even faster cycle rate. This is accomplished because the CAS signal is not used to also clear the input/output (I/O) buffer of the memory device by setting the high impedance tri-state. This independence allows for pipelined data flow in which data can be read and processed faster. In general, an extended output is accomplished by configuring a DRAM, such as a fast page mode DRAM, so that a separate signal puts the I/O buffer into the high impedance tri-state (indicating no data) when the CAS signal goes into precharge. Thus, in an EDO DRAM, the CAS precharge is not needed to clear the I/O buffer and the CAS precharge time can be considerably shortened. Consequently, data fetch time and operational cycle time can be reduced.
However, the development of these higher speed memory devices requires testers to be faster as well. Since high speed test equipment is very expensive, this requirement can significantly increase the investment in equipment and the total cost of manufacturing these devices. Furthermore, in some cases the evolution of the test equipment does not keep pace with the rapid progress in memory devices, so that a delay in production might be introduced until new, faster test equipment can be made available. Accordingly, there is great benefit in adapting the available low speed test equipment to work with higher speed memory devices in terms of both total production cost and in terms of the time to bring new memory devices to market.
For example, a M9600 tester for memory devices available from MINATO in Japan has a maximum frequency of 33 megahertz, MHz, (i.e., a minimum test cycle time of 30 nanoseconds, ns) and a usable test cycle time that can be adjusted in a range from 30 ns to 4 milliseconds. This tester is not designed to achieve an operational cycle time, i.e., a hyper page cycle time, t
HPC
, of 20 ns to 25 ns needed for a 16M DRAM EDO 50 ns/60 ns page read/write test item.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the maximum frequency limitation of a tester and to provide a method to use a low speed tester to test high speed memory devices.
The present invention is a test method for testing a semiconductor device that provides a tester which generates a plurality of general clock signals and which has a minimum test cycle time greater than an operational cycle time of the semiconductor device. Then a modulated clock signal is generated from a first general clock signal and a second general clock signal so that the modulated clock signal has a minimum cycle time no greater than the operational cycle time. The next steps include supplying the modulated clock signal to the semiconductor device as a predetermined control signal, supplying test signals to the semiconductor device as specified by a functional test item, and comparing an output of the semiconductor device to a reference value.
REFERENCES:
patent: 5610864 (1997-03-01), Manning
patent: 5805611 (1998-09-01), McClure
patent: 5933379 (1999-08-01), Park et al.
Chi Il Sik
Han Heui
Ju Ki Bong
Ryu Jae Bun
Chase Shelly A
De'cady Albert
Jones Volentine, L.L.C.
Samsung Electronics Co,. Ltd.
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