Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-09-17
1999-12-21
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
365201, G01R 3128
Patent
active
060063475
ABSTRACT:
An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.
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Churchill Jonathan F.
Finn Mark A.
Hendry Colin J.
Pancholy Ashish
Phelan Cathal G.
Beausoliel, Jr. Robert W.
Cypress Semiconductor Corporation
Iqbal Nadeem
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