Test methodology based on multiple skewed scan clocks

Details Test methodology based on multiple skewed scan clocks Test methodology based on multiple skewed scan clocks

1998-09-17

2000-05-30

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714724, 714726, G01R 3128

Patent

active

060702605

ABSTRACT:
A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.

REFERENCES:
patent: 5848075 (1998-12-01), Katayama et al.
patent: 5864564 (1999-01-01), Levitt et al.
patent: 5875153 (1999-02-01), Hii et al.

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