Test method of chips in a semiconductor wafer employing a test a

Details Test method of chips in a semiconductor wafer employing a test a Test method of chips in a semiconductor wafer employing a test a

1998-07-31

2000-11-21

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714734, 714741, G01R 3128

Patent

active

061516953

ABSTRACT:
Sample chips are tested after determining the chip layout on a semiconductor wafer so that one or plural ones of untested chips are surrounded by plural ones of the sample chips that adjoin the untested samples. A good/defective judgment on the untested chips is performed by using predicted good/defective judgment results that are statistically predicted based on results of the sample test and stored statistical data of a defect generation profile including address information that indicates defective chip locations. As a result, the good/defective judgment can be performed with high accuracy even in a case where defective chips are localized in a particular region on the wafer in a concentrated manner.

REFERENCES:
patent: 5440720 (1995-08-01), Baisuck et al.
patent: 5586046 (1996-12-01), Feldbaumer et al.
patent: 5621653 (1997-04-01), Yuzawa

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