Scan testable register file
Scan testing architectures for power-shutoff aware systems
Scan testing methods
Scan testing mode control of gated clock signals for flip-flops
Scan testing mode control of gated clock signals for memory...
Scan testing of integrated circuits with high-speed serial...
Scan testing of integrated circuits with high-speed serial...
Scan testing system for circuits under test
Scan testing using scan frames with embedded commands
Scan tests tolerant to indeterminate states when employing...
Scan verification for a scan-chain device under test
Scan-based testing of devices implementing a test clock...
Scan-bypass architecture without additional external latches
Scan-enabled method and system for testing a system-on-chip
Scan-path circuit, logic circuit including the same, and...
Scan-path flip-flop circuit for integrated circuit memory
Scanable latch circuit and method for providing a scan...
Scanable R-S glitch latch for dynamic circuits
Scannable state element architecture for digital circuits
Scanning a protocol signal into an IC for performing a...