Scan-path flip-flop circuit for integrated circuit memory

Details Scan-path flip-flop circuit for integrated circuit memory Scan-path flip-flop circuit for integrated circuit memory

2006-12-05

2006-12-05

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07146549

ABSTRACT:
A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to a normal-mode clock signal, supplying the latched first signal to the integrated circuit memory, and further latching a second signal in response to a first scan-mode clock signal. The first signal from the master latching circuit is latched in a slave latching circuit in response to the normal-mode clock signal, and the second signal from the master latching circuit is latched in the slave latching circuit in response to a second scan-mode clock signal. The slave latching circuit of each preceding flip-flop is connected to the master latching circuit of a succeeding flip-flop for shifting the second signal in response to the first scan-mode clock signal.

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