Scan testing mode control of gated clock signals for memory...

Details Scan testing mode control of gated clock signals for memory... Scan testing mode control of gated clock signals for memory...

2006-06-06

2006-06-06

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S729000

Reexamination Certificate

active

07058868

ABSTRACT:
Circuits and methods to enhance scan testing by controlling clock pulses that are provided to memory devices within an integrated circuit are provided. An integrated circuit is provided that includes a scan testing clock control circuit and a memory bypass enable contact point. The scan testing clock control circuit enables control of a clock input signal to one or more memory devices within the integrated circuit. In one embodiment the scan testing clock control circuit includes a latch, and two AND gates. A scan test mode input and a memory bypass enable input are used to determine whether the memory will be permitted to receive a clock signal. Methods for scan testing using a scan testing clock control circuit are also provided.

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patent: 6760866 (2004-07-01), Swoboda et al.
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