Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-02-15
2004-06-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S016000
Reexamination Certificate
active
06745356
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to the digital design architecture that employs scannable state elements for the testing of logic, and more particularly, to an apparatus and a method for reducing the overhead associated with scannable state elements.
2. Description of the Background Art
Digital circuit designs commonly include state elements, such as latches or flip-flops. Such designs may further employ a full scan design that advantageously provides controllability and observability of internal logic in a circuit. For designs that employ a scan, the state elements are usually scannable. The scannable state elements are further disposed within defined scan paths. During a full scan, scannable state elements may receive random data from a pseudo random pattern generator (PRPG) or deterministic scan vectors from a tester. Based on the received random data, the scannable state elements provide valid values which may be analyzed during testing.
Each scannable state element holds an internal state of a circuit. For diagnostics, it is desirable to enable scanning of state elements within a scan path so internal states can be observed and controlled. Improved controllability may be achieved by coupling a scannable state element and a multiplexor to logic. The internal nodes of the logic may be controlled by scanning in a new state value through the scannable state element. Improved observability may be achieved by coupling a scannable state element to logic. The internal nodes of the logic may be captured and scanned through the scannable state element. Without the scanning functionality, it is not possible to test logic in this manner.
Although scannable state elements are desired, there is a high overhead associated with scannability. Scannable state elements require a substantial increase in the amount of hardware, such as the number of transistors. This is understandable as modern digital design commonly employs hundreds of thousands of state elements. As technology progresses, the number of state elements will likely increase to millions of state elements. The increased hardware requires additional space. As space is a very limited commodity in circuit design, scannability becomes a costly feature. Scannable state elements further result in increased capacitive loading and an increased number of gates for testing. The increased capacitive loading and number of gates slows down scanning and reduces overall performance of the circuit design.
It would therefore be an advancement in the art to provide a digital circuit design having scanning capability while reducing the requisite overhead. It would be a further advancement in the art to provide a scannable digital circuit design with a reduced number of scannable state elements. It would be a further advancement in the art to provide such a digital circuit design while still providing observability and controllability. Such an invention is disclosed and claimed herein.
SUMMARY OF THE INVENTION
The present invention relates to an improved digital circuit design employing scannable state elements. Scannability allows for improved testing of complex logic by controlling and observing the internal nodes of the complex logic. The present invention improves scan design by sharing components of the scannable state elements.
In one embodiment a digital circuit design includes a first functional latch coupled to a first logic block to test the first logic block. The functional latch is disposed within a scan chain and receives a first scan input. A second functional latch is coupled to a second logic block to test the second logic block. The second functional latch is disposed within a second scan chain and receives a second scan input. The functional latches are coupled to a holding latch that captures content from the functional latches. By having the latches share a common holding latch, the scan design reduces overhead and space.
In another embodiment, the digital circuit design includes a first logic block and a second logic block that are coupled to a scannable state element. The scannable state element may include a functional latch and a holding latch that captures content from the functional latch. The functional latch may test the first and second logic blocks to provide controllability and observability. The functional latch is disposed within two different scan chains and receives scan inputs from both scan chains. Because the scan chains share a common functional latch, the scans must run separately to avoid a conflict. In both embodiments, the invention provides improved controllability and/or observability by sharing a common holding latch or a common scannable state element. By sharing components, the invention reduces overhead, capacitive loading, and timing delays. The invention further provides for additional space which is very limited in digital circuit architecture.
REFERENCES:
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5875346 (1999-02-01), Luick
patent: 6219811 (2001-04-01), Gruetzner et al.
patent: 6380780 (2002-04-01), Aitken et al.
De'cady Albert
Fenwick & West LLP
Gandhi Dipakkumar
LandOfFree
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