Scanable R-S glitch latch for dynamic circuits

Details Scanable R-S glitch latch for dynamic circuits Scanable R-S glitch latch for dynamic circuits

2005-06-14

2005-06-14

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C377S073000

Reexamination Certificate

active

06907556

ABSTRACT:
A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.

REFERENCES:
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patent: 6070259 (2000-05-01), Roisen et al.
patent: 6570407 (2003-05-01), Sugisawa et al.
patent: 6636996 (2003-10-01), Nowka
Abramovici, M. et al. “Design for testability” inDigital systems testing and testable design, 368-381 (1990).

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