Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-30
2008-09-23
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
07428678
ABSTRACT:
In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data between the serial link interface and a scan chain during a scan test, and for transferring data between the serial link interface and a core logic circuit of the integrated circuit, without going through the scan chain, during normal operation. Scan data may be generated and analyzed by a tester integrated circuit coupled to the integrated circuit over the serial bus.
REFERENCES:
patent: 5815509 (1998-09-01), Deng et al.
patent: 5862152 (1999-01-01), Handly et al.
patent: 6665817 (2003-12-01), Rieken
patent: 6728799 (2004-04-01), Perner et al.
patent: 7155370 (2006-12-01), Nejedlo
Ajay Khoche “Test Resource Partitioning for Scan Architectures Using Bandwidth Matching”, Oct. 2002 pp. 1.4-1 to 1.4-8, IEEE Test Resource Partitioning Workshop, Agilent Technologies, California.
Alfred L. Crouch, “Design-for-Test for Digital IC's and Embedded Core Systems” 1999, pp. 92-133, Prentice Hall PTR., New Jersey.
Gregory A. Maston, et al., “Elements of STIL Principles and Applications of IEEE Std. 1450”, 2003, pp. 200-205, Kluwer Academic Publishers, U.S.
Michael Santarini, et al. “SynTest Readies Scan-Test Data Compaction Tool”, EETimes Global News for the Creators of Technology, Sep. 2, 2002, [online][retrieved on Aug. 17, 2005]. Retrieved from the Internet; <URL:http://www.eetimes.com/story/DEG20020902S0027>.
VirtualScan “Tool Suite for Virtual Scan Synthesis and ATPG (Automatic Test Pattern Generation)”, Webpage [online][retrieved on Aug. 17, 2005]. Retrieved from the Internet:<URL:http:www.syntest.com/ProdDataSheet/Virtualscan.pdf>.
Berndt Paul D.
Larky Steven
Cypress Semiconductor Corporation
Okamoto & Benedicto LLP
Ton David
LandOfFree
Scan testing of integrated circuits with high-speed serial... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scan testing of integrated circuits with high-speed serial..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan testing of integrated circuits with high-speed serial... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3972586