Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-03
2007-07-03
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C714S030000
Reexamination Certificate
active
10861306
ABSTRACT:
A scan-path circuit is made up of cascaded flip-flops which are input/output circuits of a combinational logic circuit. In a logic circuit21which adopts a scan design test technique for simplifying a test of the same by serially shifting a test result through the flip-flops, selectors for directly connecting inputs of the respective flip-flops of the scan-path circuit to a scan input are provided. After causing all flip-flops to have identical values (either “0” or “1”), the values are shifted and outputted so that the location of a failure is specified. With this, the maximum period of time required by the test does not exceed the total of clocks for the shifting through all stages and one more stage. Thus, in addition to the checking of the presence of a failure, the location of a failure is, if necessary, specified in a short period of time.
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De'cady Albert
Harness Dickey & Pierce PLC
Sharp Kabushiki Kaisha
Trimmings John P.
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