Scan-based testing of devices implementing a test clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S729000, C714S731000

Reexamination Certificate

active

07840861

ABSTRACT:
Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. It also includes performing an inter-domain test to exercise a second subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. The dynamic fault detection test patterns can include, for example, last-shift-launch test patterns and broadside test patterns. In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.

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