Scan verification for a scan-chain device under test

Details Scan verification for a scan-chain device under test Scan verification for a scan-chain device under test

2008-06-10

2008-06-10

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

07386775

ABSTRACT:
Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

REFERENCES:
patent: 5642362 (1997-06-01), Savir
patent: 6748564 (2004-06-01), Cullen et al.
patent: 6920582 (2005-07-01), Alt et al.
patent: 7080300 (2006-07-01), Herron et al.

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