Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-16
2011-08-16
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C716S133000, C716S136000
Reexamination Certificate
active
08001433
ABSTRACT:
In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.
REFERENCES:
patent: 6782501 (2004-08-01), Distler et al.
patent: 7103816 (2006-09-01), Distler et al.
patent: 7647540 (2010-01-01), Rajski et al.
patent: 7779320 (2010-08-01), Chmelar
patent: 7779381 (2010-08-01), Chickermane et al.
patent: 2005/0149799 (2005-07-01), Hemia et al.
patent: 2008/0276140 (2008-11-01), Gemmeke et al.
patent: 2009/0135961 (2009-05-01), Gemmeke et al.
patent: 2009/0160544 (2009-06-01), Otsuga et al.
patent: 2009/0326854 (2009-12-01), Chakravadhanula et al.
patent: 2010/0153759 (2010-06-01), Singhal
Shih-Ping Lin; Chung-Len Lee; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen-Ching Wu; , “A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 15, No. 7, pp. 767-776, Jul. 2007 doi: 10.1109/TVLSI.2007.899232.
Jia Li; Xiao Liu; Yubin Zhang; Yu Hu; Xiaowei Li; Qiang Xu; , “On capture power-aware test data compression for scan-based testing,” Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on , vol., no., pp. 67-72, Nov. 10-13, 2008 doi: 10.1109/ICCAD.2008.4681553.
Xijiang Lin; Rajski, J.; , “Test Power Reduction by Blocking Scan Cell Outputs,” Asian Test Symposium, 2008. ATS '08. 17th , vol., no., pp. 329-336, Nov. 24-27, 2008 doi: 10.1109/ATS.2008.33.
N. Badereddine; Z. Wang; P. Girard; K. Chakrabarty; S. Pravossoudovitch; C. Landrault; , “Power-Aware Test Data Compression for Embedded IP Cores,” Test Symposium, 2006. ATS '06. 15th Asian , vol., no., pp. 5-10, Nov. 2006 doi: 10.1109/ATS.2006.260985.
C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, A. Ferko, B. Keller, D. Scott, T. Onodera and B. Koenemann, “Extending OPMISR beyond 10x Scan Test Efficiency,” Design & Test of Computers, IEEE, Sep.-Oct. 2002, pp. 65-73.
C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller and B. Koenemann, “OPMISR: The Foundation for Compressed ATPG Vetors,” Proc IEEE International Test Conf (ITC 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 748-757.
Y. Bonhomme et al., “A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores,” Proc. 10th Asian Test Symp. (ATS 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 253-258.
A. Chandra and K. Chakrabarty, “Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip,” Proc. 38th ACM/IEEE Design Auto. Conf. (DAC 01), ACM Press, New York, 2001, pp. 166-169.
V. Chickermane, B. Foutz, and B. Keller, “Channel Masking Synthesis for Efficient On-Chip Test Compression,” Proc. IEEE International Test Conf (ITC 04), IEEE CS Press, Los Alamitos, Calif., 2004, pp. 452-461.
F. Corno et al., “A Test Pattern Generation Methodology for Low Power Consumption”, in Proc. 16th VLSI Test Symp. (VTS 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 453-459.
V. Dabholkar, S. Chakravarty, I. Pomeranz, and S.M. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. on Computer-Aided Design, vol. 17, No. 12, pp. 1325-1333, Dec. 1998.
P. Girard et al., “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation” in Proc. 9th Great Lakes Symp. on VLSI (GLS-VLSI 99), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 24-27.
P. Girard et al., “Reducing Power Consumption during Test Application by Test Vector Ordering,” Proc. Int'l Symp. Circuits and Systems (ISCAS 98), Part II, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 296-299.
J. Li, Y. Hu, and X. Li, “A Scan Chain Adjustment Technology for Test Power Reduction,” Proc. 15th Asian Test Symp, IEEE, 2006, pp. 11-16.
J. Rajski, et. al., “Embedded Deterministic Test for Low-Cost Manufacturing Test”, Proc IEEE International Test Conf (ITC 01), IEEE CS Press, Los Alamitos, Calif., 2002, pp. 301-310, 2002.
R. Sankaralingam, R. Oruganti, and N.A. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation” in Proc. 18th VLSI Test Symp. (VTS 00), IEEE CS Press, Los Alamitos, Calif., 2000, pp. 35-42.
O. Sinanoglu and A. Orailoglu, “Modeling Scan Chain Modifications for Scan-in Test Power Minimization”, ITC International Test Conference, Paper 24.1, IEEE 2003, pp. 602-611.
S. Wang and S.K. Gupta, “ATPG for Heat Dissipation Minimization During Test Application,” IEEE Trans. Computers, vol. 47, No. 2, Feb. 1998, pp. 256-262.
Bhatia Sandeep
Chickermane Vivek
Foutz Brian
Gallagher Patrick
Britt Cynthia
Cadence Design Systems Inc.
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Scan testing architectures for power-shutoff aware systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scan testing architectures for power-shutoff aware systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan testing architectures for power-shutoff aware systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2628543