Scan testing mode control of gated clock signals for flip-flops

Details Scan testing mode control of gated clock signals for flip-flops Scan testing mode control of gated clock signals for flip-flops

2006-08-08

2006-08-08

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07089471

ABSTRACT:
Circuits and a method to enhance scan testing by controlling clock pulses that are provided to flip-flops within an integrated circuit are provided. An integrated circuit is provided that includes a scan testing clock control circuit for flip-flops. The scan testing clock control circuit enables control of a clock input signal to one or more flip-flops within the integrated circuit. In one embodiment, a scan testing clock control circuit can be used to ensure that a flip-flop receives a clock input signal during scan testing. In one embodiment the scan testing clock control circuit includes a latch, and an AND gate. A method for scan testing using a scan testing clock control circuit for flip-flops is also provided.

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