Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-23
2001-05-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06240536
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits and, more particularly, to a latch circuit which may be scan tested.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit devices may be designed to allow simplified failure diagnostic testing. One design technique which allows such testing is referred to as scan path design. In scan path design, circuit elements are arranged to form a series of linked shift registers for diagnostic testing purposes. The bit shift route through these linked shift registers is referred to as a scan path. A bit shift operation is used to serially supply diagnostic test data to each of the linked circuit elements.
Each circuit element in the scan path includes a scan input, in addition to the regular data input and data output for the circuit element. During a scan test operation for a circuit element, the normal operation of the circuit element is inhibited. With scan testing enabled, a signal applied to the scan input of a typical scanable circuit element produces a corresponding scan out signal at the circuit element's data output. A scan out signal may also be provided at a separate scan output. The scan out signal produced by the circuit element in response to the scan in signal should coincide with the signal which would have resulted in the normal operation of the circuit. Failure of the circuit element to produce the predicted scan out signal indicates a failure of the circuit element.
Although the ability to scan test circuit elements in an integrated circuit simplifies diagnostic testing, there have been drawbacks to scan path design. One such drawback is the effect of the additional scan test circuitry on the performance of a circuit element in normal operation. Scan test circuitry associated with a particular circuit element may add substantial capacitance to the circuit element critical path. This added capacitance results in a substantial reduction in the performance of the circuit element in normal operation.
SUMMARY OF THE INVENTION
It is an object of invention to provide a scanable latch circuit in which the additional scan circuitry does not substantially impair the performance of the circuit in normal operation. It is also an object of invention to provide a method for providing a scan output from a latch circuit without substantially incurring a performance penalty in the normal operation of the latch circuit.
A latch circuit according to invention applies scan input data through a feedback path which is isolated from the latch circuit critical path. “Isolated” in this sense means that the feedback path is not directly connected to the circuit critical path. The signal on the feedback path is not directly applied to the circuit critical path but is available for controlling the signal on the circuit critical path. A separate scan out signal is also preferably derived from a signal in the latch circuit feedback path. By scan testing through the isolated feedback path, the scan circuitry adds substantially no capacitance to the latch circuit critical path.
The latch circuit includes a latch data input node connected to a data output node through a latch input component. The latch data output node comprises the circuit critical path. A feedback path connected to the output node is isolated from the data output node by first and second isolating components, preferably inverter circuits. A scan enable component, which may comprise a pass gate arrangement, is responsive to a scan enable signal to selectively decouple a first feedback node from a second feedback node in the feedback path thereby breaking the feedback path to facilitate scan testing. In normal operation, the scan enable component couples the first and second feedback nodes allowing the latch circuit to operate normally.
When a scan enable signal is applied to the scan enable component, thereby decoupling the first and second feedback nodes, a scan input component connected to the second feedback node applies a scan input signal to control the signal on the latch circuit data output node. That is, the scan input component applies scan in test data through the second feedback node, a point isolated from the latch circuit critical path. Also, the preferred form of the invention includes a scan output component which, when scan testing is enabled, utilizes a signal on the feedback path to develop a separate scan out signal. The preferred scan output component is controlled by a scan clock to hold the separate scan out signal independently of the signal at the data output node.
By applying the scan in test data through the isolated feedback path, the scan circuitry does not add capacitance to the latch circuit critical path. Also, since the scan output component uses a signal in the feedback path to produce the scan out signal, the scan output circuitry also does not add capacitance to the latch circuit critical path. Furthermore, the preferred scan clock arrangement associated with the scan out circuitry provides an additional functional output when the circuit is not operating in scan test mode.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.
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LeBlanc Johnny James
Mikan, Jr. Donald George
Culbertson Russell D.
De'cady Albert
International Business Machines - Corporation
Lamarre Guy
McBurney Mark
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