Scan-bypass architecture without additional external latches

Details Scan-bypass architecture without additional external latches Scan-bypass architecture without additional external latches

1997-05-16

1999-07-20

Beausous, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

365201, G01R 3128

Patent

active

059251433

ABSTRACT:
A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components.

REFERENCES:
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4009348 (1977-02-01), Tate
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 5048021 (1991-09-01), Jarwala et al.
patent: 5056093 (1991-10-01), Whestel
patent: 5084847 (1992-01-01), Whestel, Jr.
patent: 5150044 (1992-09-01), Hashizume et al.
patent: 5257267 (1993-10-01), Ishizaka
patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5329533 (1994-07-01), Lin
patent: 5331643 (1994-07-01), Smith
patent: 5430735 (1995-07-01), Sauerwald et al.
patent: 5448575 (1995-09-01), Hashizume
patent: 5448576 (1995-09-01), Russell
patent: 5473617 (1995-12-01), Farwell
patent: 5477545 (1995-12-01), Huang
patent: 5491666 (1996-02-01), Sturges
patent: 5497378 (1996-03-01), Amini et al.
patent: 5615217 (1997-03-01), Horne et al.
patent: 5627840 (1997-05-01), Hundertmark et al.
patent: 5631911 (1997-05-01), Whetsel, Jr.
patent: 5646422 (1997-07-01), Hashizume
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 5677915 (1997-10-01), Whetsel
Culican EF, Diepenbrock JC and Ting YM. Shift Register Latch for Package Testing in Minimum Area and Power Dissipation. IBM Technical Disclosure Bulletin, 24(11A):5598-5600.
McAnney WH. Bypass Latch Control of Long Shift Register Strings. IBM Technical Disclosure Bulletin , 32(7):474-478.
Moser, JJ. LSSD Scan Path Truncated to Minimum Length For Testing. IBM Technical Disclosure Bulletin, 25(12):6547-6549.

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