Scan testing system for circuits under test

Details Scan testing system for circuits under test Scan testing system for circuits under test

2007-11-13

2010-06-15

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S814000

Reexamination Certificate

active

07739568

ABSTRACT:
A scan test circuit includes tester inputs that receive scan test data. Scan chains are coupled to the tester inputs. The tester outputs are coupled to the scan chains and provide output test data based on the scan test data. A first clock generates a first clock signal. A sampling circuit samples each of the tester outputs at least twice per clock cycle of the first clock signal.

REFERENCES:
patent: 7099783 (2006-08-01), Hasegawa et al.
patent: 7237162 (2007-06-01), Wohl et al.
patent: 7512851 (2009-03-01), Wang et al.

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