Master-slave-type scanning flip-flop circuit for high-speed...

Details Master-slave-type scanning flip-flop circuit for high-speed... Master-slave-type scanning flip-flop circuit for high-speed...

2005-11-22

2005-11-22

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S202000, C365S154000

Reexamination Certificate

active

06968486

ABSTRACT:
A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master latch and a slave latch each for temporarily holding an input signal, a first scan controller, a clock controller, and a second scan controller. The first scan controller receives an output signal from the master latch and outputs the received output signal in synchronism with a scan clock which is a clock for testing the semiconductor integrated circuit device, when the semiconductor integrated circuit device is tested. The clock controller receives an output signal from the first scan controller and outputs the received output signal to the slave unit in synchronism with a predetermined clock when in a normal mode of operation. The second scan controller has an input terminal connected to an output terminal of the first scan controller, and outputs a scan-out signal corresponding to a scan-in signal which is an input signal for testing the semiconductor integrated circuit device, in synchronism with the scan clock when the semiconductor integrated circuit device is tested.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5633606 (1997-05-01), Gaudet et al.
patent: 63-253272 (1988-10-01), None
patent: 63253272 (1988-10-01), None
patent: 05-160682 (1993-06-01), None
patent: 5-267999 (1993-10-01), None

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