Measurement circuit and method for serially merging...

Details Measurement circuit and method for serially merging... Measurement circuit and method for serially merging...

2007-02-27

2007-02-27

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S776000

Reexamination Certificate

active

11075790

ABSTRACT:
Provided are a measurement circuit and method for serially merging single-ended signals to analyze them. To analyze two differential signals probed from a DUT, that is, DP and DM signals, the measurement circuit detects DP data from which its DC portion has been removed and DM data from which its DC portion has been removed, stores the two data signals in a memory, and then serially merges the two data signals stored in the memory without distorting them. The measurement circuit divides the serially merged signal at a predetermined period and overlaps the divided signals to generate eye diagram data and analysis data including crossover voltages, rising time, falling time and so on.

REFERENCES:
patent: 6157693 (2000-12-01), Jayaraman
patent: 6675117 (2004-01-01), Adam et al.
patent: 6694462 (2004-02-01), Reiss et al.
patent: 6710594 (2004-03-01), Eunkyu et al.
patent: 6909980 (2005-06-01), Fernando
patent: 6941649 (2005-09-01), Goergen
patent: 2004/0019458 (2004-01-01), Jang

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