Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-03-18
2008-03-18
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S709000
Reexamination Certificate
active
11022023
ABSTRACT:
A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”) and logic for activating a match_OR signal when at least one of one or more designated bits of the selected N-bit portion of the data is a logic 1 or if there are no designated bits.
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EP Search Report dated Sep. 16, 2005 (1 pg.).
Britt Cynthia
Hewlett--Packard Development Company, L.P.
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