Mask network design for scan-based integrated circuits

Details Mask network design for scan-based integrated circuits Mask network design for scan-based integrated circuits

2006-04-18

2006-04-18

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S727000

Reexamination Certificate

active

07032148

ABSTRACT:
A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells220from propagating through the scan chains221for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit207in a selected scan-test mode232or selected self-test mode. The scan-based integrated circuit207contains a plurality of scan chains221, a plurality of pattern generators208, a plurality of pattern compactors213, with each scan chain221comprising multiple scan cells220, 222coupled in series. The method and apparatus further includes an output-mask controller211and an output-mask network212embedded on the scan data input path of second selected scan cells222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller211and the set/reset controller.

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Mitra et al; “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” Proc., ITC Intl. Test Conf., 2002.
Mitra et al: “XMAX: X-Tolerant Architecture for MAXimal Test Compression,” Proc. Intl. Conf. on Computer Design, pp. 326-330, 2003.

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