Means scanning scan path parts sequentially and capturing...

Details Means scanning scan path parts sequentially and capturing... Means scanning scan path parts sequentially and capturing...

2006-05-23

2006-05-23

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

07051257

ABSTRACT:
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator102, compactor106, and controller110remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path502, to insert scan paths A506, B508and C510, and the insertion of an adaptor circuit504in the control path114between controller110and scan path502.

REFERENCES:
patent: 6158032 (2000-12-01), Currier et al.
patent: 6316959 (2001-11-01), Onodera
patent: 6327685 (2001-12-01), Koprowski et al.
patent: 6594802 (2003-07-01), Ricchetti et al.

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