Master controller architecture

Details Master controller architecture Master controller architecture

2007-12-11

2007-12-11

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

10999720

ABSTRACT:
A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.

REFERENCES:
patent: 5717948 (1998-02-01), Michalina
patent: 6512709 (2003-01-01), Nakahara et al.
patent: 7216277 (2007-05-01), Ngai et al.

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