Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-27
2001-02-06
Tu, Trinh L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S820000, C714S736000, C714S738000
Reexamination Certificate
active
06185708
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor integrated circuits, and more particularly, to a maintenance free semiconductor test system in which a user of the test system does not need to take any measures or maintenance works against the failures or defects in the semiconductor test system or to recognize the results of such maintenance works.
BACKGROUND OF THE INVENTION
Because the recent semiconductor integrated circuits become more and more complicated and high level, recent semiconductor test systems for testing such integrated circuits also have become more and more complicated and large scale. For example, the number of pins of a recent semiconductor device under test (hereinafter sometimes referred to as “DUT”) extends to as many as 1,000, which requires that a semiconductor test system (test system) for testing such a DUT be equipped 1,000 or more test channels (hereafter may also be referred to as “tester pins”). Each tester channel includes a pattern generator, a timing generator, a test waveform formatter, as well as a driver and a comparator to independently supply a desired test pattern to a corresponding pin of the DUT to evaluate the performance at the pin of the DUT.
FIG. 1
is a schematic block diagram showing an example of such a test system. In this example, the test system is illustrated by a combination of basic functional blocks, and thus, each test channel (tester pin) noted above is not shown. In
FIG. 1
, the test system is comprised of a work station
12
, a test controller
14
, a test unit
15
, and a test head
16
for testing a device under test
18
. The work station
12
functions as a user interface and operates under an operating system such as UNIX. The work station
12
may be connected to a network
11
to establish a test system network having a plurality of test systems.
The tester controller
14
is an exclusive processor provided in the test system to control various operations of the test system. The test unit
15
is to provide a test pattern to the device under test and is formed with a pattern generator, a timing generator, a wave formatter and the like. The test head
16
is comprised of a driver for providing a test pattern to the device under test
18
with a predetermined amplitude and threw rate, and a comparator for detecting an output signal level of the device under test
18
and comparing the detected signal with the expected value data. In the above noted configuration of the test system, the test unit
15
and the test head
16
are provided for each tester pin (test channel), the number of the tester pins is the same or greater than the maximum number of pins of the device to be tested.
As in the foregoing, because the test system has a circuit configuration of complicated and large scale, an overall test system of today is a very large system having a large number of components. As a consequence, a test system cannot be completely immune to occurrences of failures and must be prepared to any defects. For example, when a defect is discovered in a certain tester pin of the test system when using the test system or by running a self diagnostic test, a maintenance process will be conducted in which the defective tester pin may be replaced with an interchangeable tester pin (supplemental tester pin).
In such a replacement of components in the test system, however, it is not preferable if the user of the test system must modify the test program for the test system or must prepare a new test program reflecting the changes in the test system, or must keep the data regarding the hardware structural changes in the test system, because it is too burdensome to the user. Therefore, there is a need that the user can use the test system in the same manner as before without worrying about any changes resulted from the maintenance work.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a maintenance free test system which does not require a user to know the changes in the inner hardware structure resulted from the maintenance of the test system.
It is another object of the present invention to provide a maintenance free test system which does not require a user to modify the test program or to use other test program even though there is a change as a result of the maintenance of the test system.
It is a further object of the present invention to provide a maintenance free test system in which the data concerning the changes in the internal hardware or the maintenance history of the test system and the like is managed by a centralized CPU system provided separately from the test system and connected with the test system through a network and system monitor.
It is a further object of the present invention to provide a test system which does not require any changes in the test program even when there arises a failure in a tester pin of the test system by replacing the defective tester pin with a supplemental tester pin and the information regarding the pin change is recorded in the data table of a pin assignment converter.
It is a further object of the present invention to provide a test system which has a pin assignment converter for storing table data showing the relationship between logical pin numbers and physical pin numbers as well as table data showing the relationship between the physical pin numbers and the pin numbers actually used by replacing the defective tester pins.
In the present invention, a test system having a large number of test channels (tester pins) corresponding to the number of terminal pins of a semiconductor device to be tested, includes:
a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns;
a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller;
a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit;
a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals from the semiconductor device and comparing the output levels with the expected values;
a switch circuit provided between the test head and the semiconductor device for changing the defective tester pin to the supplemental tester pin based on the conversion data from the pin assignment converter; and
a system monitor for monitoring data concerning changes in the tester pins in the test system and modifications involving maintenance works and managing the data thereof.
In the further aspect of the present invention, the test system further includes a work station which functions as a user interface. The user provides various test conditions through the work station to the test program to execute the semiconductor device testing.
When the user sets the test conditions in the test program through the work station, the pin assignment converter produces conversion data which converts the logical tester pin number specified by the user in the test program to the corresponding physical tester pin number.
According to the present invention, the user of the test system does not need to know the changes in the inner hardware structure resulted from the maintenance of the test system. It is not necessary for the user to modify the test program or to use other test program even if there are changes in the inner structure of the test system as a result of the maintenance of the test system. Further, in the test system of the present invention, the data concerning the changes in the internal hardware or the maintenance history of the test system and the like is managed by a centralize
Advantest Corp.
Muramatsu & Associates
Tu Trinh L.
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