Mapping logic for controlling loading of the select ram of...

Details Mapping logic for controlling loading of the select ram of... Mapping logic for controlling loading of the select ram of...

2006-05-31

2008-09-02

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C702S118000, C702S123000

Reexamination Certificate

active

07421632

ABSTRACT:
Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.

REFERENCES:
patent: 6130546 (2000-10-01), Azizi
patent: 6671844 (2003-12-01), Krech et al.
patent: 6963208 (2005-11-01), Fukasawa et al.
patent: 2002/0049554 (2002-04-01), Miller
patent: 2002/0173926 (2002-11-01), McCord

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