Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-01-27
2001-11-27
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06324664
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The disclosed invention generally relates to scan path testing circuitry, and more particularly to scan path testing circuitry for applications wherein the system clock frequency is constant and uninterrupted while the test clock from external test equipment may be of a different frequency, asynchronous or discontinuous relative to the system clock.
BACKGROUND OF THE INVENTION
Digital integrated circuit devices often employ special circuits to aid testability so as to make the operation of testing a digital device simpler, more efficient and more effective.
A very common built-in test circuit is a scan path or chain by which the bistable elements (flip-flops and/or latches) within a digital device are connected into a shift register called a scan path or scan chain. With the digital device in scan mode, an input pattern is serially scanned into the bistable elements (i.e., serially shifted into the bistable elements). The digital device is then operated in the normal mode for one clock period, which causes the bistable element contents to act as inputs to the internal combinatorial logic, and causes subsequent response values to be stored in the bistable elements. The digital device is again placed in the scan mode to allow the response pattern stored in the bistable elements to be serially scanned out (i.e., serially shifted out) and compared with the correct response.
In the scan mode, input patterns are provided by external test equipment which also receives the response patterns shifted out of the storage elements of a scan path. Typically, the input patterns and response patterns are communicated over a common serial test bus, as for example specified by the IEEE Standard 1149.1 for a Standard Test Access Port. Often the serial scanning by the external test equipment must be performed at a test clock frequency that is different from and/or asynchronous relative to the system clock frequency at which the device under test performs its operational functions. Also, the test clock could be discontinuous.
As a result of these characteristics of the test clock frequency of test equipment, ASICs typically do not use dynamic logic, which is characterized by the need to be continuously refreshed, for example by receipt of a clock pulse at a minimum specified rate, in order to maintain data stored in memory. The advantage of dynamic logic include smaller size, lower power, and higher speed performance as compared to static logic (in which the last memory state is held indefinitely long in the absence of a clock).
U.S. Pat. No. 5,181,191, W.D. Farwell, describes a technique for testing integrated circuits (ICs) at higher clock speeds than the clock speed provided by test equipment. This supports a known technique for testing dynamic logic of ensuring that the chip clock meet a maximum clock-to-clock period. However, this technique requires that the test clock and chip clock be synchronously related, and cannot be done at all for some forms of external test equipment.
There is accordingly a need for a scan test circuit that employs a continuous system clock and a test clock that can be discontinuous and/or asynchronous.
SUMMARY OF THE INVENTION
The subject invention is a test circuit that includes a scan path having serially coupled scan flip-flops that are clocked by a system clock signal, an index counter clocked by the system clock for providing an index output for tracking data in the scan path, a control circuit clocked by a test clock signal for receiving scan input data from an external source and for providing output data to the external source, an input memory for receiving scan input data from the control circuit, an output memory for receiving the output of the scan path, and a selection circuit having a first input for receiving the output of the scan path, a second input for receiving scan input data from the input memory, and an output connected to the input of the scan path. The selection circuit is responsive to the control circuit for providing a selection circuit output that comprises (a) a replica of the i
th
scan input data bit when the i
th
scan input data bit is available at the input memory and the index counter indicates that the i
th
scan input data is ready for receipt into the scan path, and (b) otherwise a replica of the output of the scan path. The control circuit further samples the output memory.
In accordance with a more specific aspect of the invention the scan flip-flops of the scan path comprise dynamic logic. The disclosed invention advantageously allows for the testing of dynamic logic in ASICs and other ICs with simple test equipment which may not be otherwise designed to support dynamic testing.
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Farwell William D.
Stokes Robert L.
Alkov Leonard A.
Chase Shelly A
De'cady Albert
Lenzen, Jr. Glenn H.
Raytheon Company
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