Handling a 1-hot multiplexer during built-in self-testing of...
Hardware tracing/logging for highly integrated embedded controll
Hardware verification scripting
Hierarchical access of test access ports in embedded core...
Hierarchical built-in self-test for system-on-chip design
Hierarchical creation of vectors for quiescent current...
Hierarchical test access port architecture for electronic...
Hierarchical test circuit structure for chips with multiple...
Hierarchical test response compaction for a plurality of...
Hierarchically-controlled automatic test pattern generation
High speed ATPG testing circuit and method
High speed boundary scan design
High speed built-in self-test circuit for DRAMS
High speed capture and averaging of serial data by...
High speed double data rate JTAG interface
High speed interconnect circuit test method and apparatus
High speed LSI spectral analysis testing apparatus and method
High speed pattern generating method and high speed pattern gene
High speed sink/source register to reduce level sensitive...
High speed test pattern evaluation apparatus