Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-03-01
2011-03-01
Beausoliel, Robert (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S734000, C714S735000
Reexamination Certificate
active
07900107
ABSTRACT:
The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.
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Chen Wang-Chin
Kifli Augusli
Beausoliel Robert
Faraday Technology Corp.
Hsu Winston
Margo Scott
Merant Guerrier
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