High speed interconnect circuit test method and apparatus

Details High speed interconnect circuit test method and apparatus High speed interconnect circuit test method and apparatus

2006-07-04

2006-07-04

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07073111

ABSTRACT:
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

REFERENCES:
patent: 6173428 (2001-01-01), West
patent: 6418545 (2002-07-01), Adusumilli
patent: 6829730 (2004-12-01), Nadeau-Dostie et al.

Affiliated with

Also associated with

Rating

High speed interconnect circuit test method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed interconnect circuit test method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed interconnect circuit test method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3611801