Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-02
2002-02-26
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06351835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the testing of LSI devices, and more specifically to a testing apparatus and method for an integrated circuit device by observing spectral components of a source current when the device is activated by test signals.
2. Description of the Related Art
Japanese Laid-Open Patent Specification 09-211088 discloses an LSI testing apparatus by observing the power spectral component of a source current flowing into a device under test when the device is activated in response to test signals of different patterns which are generated in repeated sequences of period T. The power spectral component is one that occurs at the fundamental frequency 1/T.
It is important, however, to perform an LSI testing in as short a time as possible and with as low a cost as possible from the viewpoint of quantity production. Since the time taken for a spectral analyzer to perform a testing on an LSI device is usually several tens of seconds, there exists a need to provide an LSI testing apparatus capable of operating at high speed.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high speed LSI spectral analysis testing apparatus and method.
Another object of the present invention is to provide a high precision LSI spectral analysis testing apparatus and method.
According to one aspect of the present invention, there is provided a testing apparatus comprising a test sequence generator for producing at least one sequence of test signals each having a different test pattern, and a source current sensor for detecting a source current flowing from a power voltage source to an integrated circuit device under test when the device is subjected to the sequence of test signals. Counter circuitry is provided for defining a window period equal to at least one sequence of the test signals. Analog-to-digital converter circuitry is arranged to sample the source current of the device during the window period and quantize sampled values of the source current to digital samples. A discrete Fourier transform (DFT) analyzer is provided for analyzing the digital samples to produce a plurality of spectral values at frequencies k/T, where T represents the period of said sequence and k is an integer equal to or greater than unity. Decision circuitry makes a decision on the analyzed spectral values using a plurality of reference spectral values.
According to another aspect, the present invention provides a testing method comprising the steps of generating at least one sequence of test signals each having a different test pattern, subjecting an integrated circuit device to the sequence of test signals so that the device consumes a source current supplied from a power voltage source, detecting the source current, defining a window period equal to at least one sequence of the test signals, sampling the source current of the device during the window period and quantizing sampled values of the source current to digital samples, analyzing the digital samples by using a discrete Fourier transform analyzer and producing a plurality of spectral values at frequencies k/T, where T represents the period of said sequence and k is an integer equal to or greater than unity, and making a decision on the analyzed spectral values using a plurality of reference spectral values.
Since the detected source current is sampled and quantized within a window period corresponding to at least one sequence of the test signals, the processing time necessary for the DFT analyzer to produce the spectral components is reduced significantly. Because of this high speed spectral analysis, the level of precision of the testing apparatus can be improved by setting the window size equal to an integral multiple of the sequence period to repeatedly apply the same test sequences to the device under test to produce a number of sequences of digital samples, and averaging the digital samples before or after the spectral analysis is performed by the DFT. A further improvement on the precision of the testing apparatus is achieved by subjecting the device under test to repeated sequences of the test signals before the detected source current is sampled. This stabilizes the device to a consistent active state.
REFERENCES:
patent: 3881097 (1975-04-01), Lehmann et al.
patent: 5633595 (1997-05-01), Ueda et al.
patent: 6047393 (2000-04-01), Yamada
patent: 9-211088 (1997-08-01), None
Chung Phung M.
NEC Corporation
Young & Thompson
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