Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-03-26
1999-12-21
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714743, G01R 3128
Patent
active
060063491
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a high speed pattern generating method for generating test pattern signals at high speed and a high speed pattern generator using this method which are useful in application thereof to a semiconductor device testing apparatus or the like, the semiconductor device testing apparatus being arranged to test a semiconductor device formed as a semiconductor integrated circuit (IC), for instance, an IC memory, as to whether it is conformable (pass) article or unconformable (failure) article.
BACKGROUND ART
FIG. 1 shows an example of a semiconductor device testing apparatus conventionally used for testing a semiconductor device such as an IC memory. As shown in the drawing, this semiconductor device testing apparatus includes a pattern generator 100, a data selector 200, a device under test, for example, an IC 300, and a logical comparator 400. The pattern generator 100 comprises a sequence control part 110 and a pattern generating part 120.
The sequence control part 110 comprises, as shown in FIG. 2, a program counter controller 111, a program counter 112, an instruction memory 113, a loop counter 114 and an initial value storing register 115. The instruction memory 113 comprises a sequence control instruction storage area 113A and a pattern generating instruction storage area 113B, and these storage areas 113A and 113B are accessed by an address signal supplied from the program counter 112. When the sequence control instruction storage area 113A is accessed, a sequence control instruction is read out from the sequence control instruction storage area 113A and then this sequence control instruction is supplied to the program counter controller 111 to be decoded therein and an address to be accessed next is determined. This address is sent to the program counter 112 from the program counter controller 111 and the program counter 112 supplies an address signal for accessing the determined address to the instruction memory 113. Then, a sequence control instruction to be next executed is read out from the instruction memory 113. In such a way, every time one of the sequence control instructions is sequentially read out from the instruction memory 113, the program counter controller 111 determines an address to be next accessed in accordance with a control instruction written in that sequence control instruction. The above operation is repeated so that a pattern generating instruction is read out from the pattern generating instruction storage area 113B.
One of the reasons why a system for reading out a pattern generating instruction while determining an address to be next accessed in accordance with a sequence control instruction is used as described above is that in case of using a system for programming pattern generating instructions one step by one step to generate pattern signals, for example, there occurs a trouble in the system that the program becomes extensive and lengthy and hence a large amount of work and time are required for the programming.
Therefore, a programming method for generating a predetermined test pattern a predetermined number of times using a loop instruction is generally employed. In this method, at starting time of a pattern generation, the number of loop times etc. are stored in the initial value storing register 115 for each loop instruction and when a loop instruction is executed, the number of loop times is counted by the loop counter 114. When the loop instruction is executed a predetermined number of times, the execution of the loop instruction is terminated and then the process moves to an execution of the next loop instruction.
A pattern generating instruction read out from the pattern generating instruction storage area 113B is supplied to a pattern generating part 120 and the pattern generating part 120 generates a test pattern signal and an address signal in accordance with the pattern generating instruction.
The data selector 200 selects an address signal and a data signal etc. to be applied to the IC under test 300 from the
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Advantest Corporation
Nguyen Hoa T.
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