Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-21
2006-11-21
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S013000
Reexamination Certificate
active
07139955
ABSTRACT:
Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.
REFERENCES:
patent: 5381344 (1995-01-01), Rohrbaugh et al.
patent: 5390131 (1995-02-01), Rohrbaugh et al.
patent: 5400263 (1995-03-01), Rohrbaugh et al.
patent: 5495578 (1996-02-01), Rohrbaugh et al.
patent: 5831996 (1998-11-01), Abramovici et al.
patent: 5905986 (1999-05-01), Rohrbaugh et al.
patent: 6070261 (2000-05-01), Tamarapalli et al.
patent: 6178533 (2001-01-01), Chang
patent: 6234689 (2001-05-01), Rohrbaugh et al.
patent: 6370677 (2002-04-01), Carruthers et al.
patent: 6396312 (2002-05-01), Shepston et al.
patent: 6607651 (2003-08-01), Stiller
patent: 6883128 (2005-04-01), Kang et al.
Kim, et al., “Sequential Test Generators: Past, Present and Future,” Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53706, Jul. 2, 1998, Revised Jul. 23, 1998.
Dr. Daniel C. Hyde, CSCI 320 Computer Architecture Handbook on Verilog HDL,: Computer Science Department, Bucknell University, Lew isburg, PA 17837, Aug. 25, 1995, Updated Aug. 23, 1997.
Rearick Jeff
Rohrbaugh John G
Avago Technologies General IP (singapore) Pte. Ltd.
Tu Christine T.
LandOfFree
Hierarchically-controlled automatic test pattern generation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hierarchically-controlled automatic test pattern generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchically-controlled automatic test pattern generation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3674516