Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-12-23
2000-09-12
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714733, G01R 3128
Patent
active
061192546
ABSTRACT:
A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.
REFERENCES:
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 5608867 (1997-03-01), Ishihara
patent: 5784712 (1998-07-01), Byers et al.
patent: 5850512 (1998-12-01), Song
Assouad Nicolas C.
Dyer David L.
Lin Wen
Galanthay Theodore E.
Jorgenson Lisa K.
Kubida William J.
Nguyen Hoa T.
STMicroelectronics N.V.
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