Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-04-26
2005-04-26
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
06886121
ABSTRACT:
A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks are a socket access port (SAP) controller. Test operation is transferred downward and upwards within said hierarchical structure.
REFERENCES:
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 5428624 (1995-06-01), Blair et al.
patent: 5477548 (1995-12-01), Beenker et al.
patent: 5513189 (1996-04-01), Savage
patent: 5627842 (1997-05-01), Brown et al.
patent: 5774474 (1998-06-01), Narayanan et al.
patent: 5828824 (1998-10-01), Swoboda
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 6012155 (2000-01-01), Beausang et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6173428 (2001-01-01), West
patent: 6191603 (2001-02-01), Muradali et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6292929 (2001-09-01), Scepanovic et al.
patent: 6311302 (2001-10-01), Cassetti et al.
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6378093 (2002-04-01), Whetsel
patent: 6381717 (2002-04-01), Bhattacharya
patent: 6408413 (2002-06-01), Whetsel
patent: 6587981 (2003-07-01), Muradali et al.
patent: 6631504 (2003-10-01), Dervisoglu et al.
Dervisoglu, Bulent, et al., “A Novel Approach for Designing Hierarchical Test Access Controller for Embedded Core Designs in an SoC Environment”.
Whetsel, Lee, “An IEEE 1149.1 Based Test Access Architecture For IC's With Embedded Cores,” Proceedings International Test Conference 1997, pp. 69-78.
Bhattacharya, Debashis, “Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit,” Proceedings 16thIEEE VLSI Test Symposium, Apr. 26-30, 1998, pp. 8-14.
Bhattacharya, Debashis, “Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller,” Proceedings 17thIEEE VLSI Test Symposium, Apr. 25-29, 1999, pp. 467-472.
B.I. Dervisoglu, A Unified DFT Architecture for use with IEEE 1149.1 and VISA/IEEE P1500 Complaint Test Access Controllers, DAC2001, Las Vegas, Nevada Jun. 18-22, 2001, pp 53-58
Cooke Laurence H.
Dervisoglu Bulent
Bingham & McCutchen LLP
Britt Cynthia
Cadence Design Systems Inc.
DeCady Albert
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