Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-16
2000-09-26
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, G01R 3128
Patent
active
061254649
ABSTRACT:
An integrated circuit with boundary scan includes core circuitry having at least one system data output. Boundary scan logic is used to control the integrated circuit to operate in a test mode or in a system mode. The boundary scan logic includes a test data line, a shift signal line, and a mode signal line. At least one output boundary scan cell having a boundary scan multiplexer is provided. The boundary scan multiplexer includes a control input coupled to the shift signal line, a first input coupled to receive a system data signal, and a second input coupled to the test data line. The boundary scan cell further includes a first output data register having an input coupled to an output of the boundary scan multiplexer. At least one output cell including an output data multiplexer is also included. The output data multiplexer includes a control input coupled to the mode signal line and includes as inputs the system data output line and an output of the first output data register. The output cell further includes an output buffer coupling an output of the output data multiplexer to a pin of the integrated circuit. In accordance with principles of the present invention, the output boundary scan cell and the output cell are separate from each other.
REFERENCES:
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 4942577 (1990-07-01), Ozaki
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5130647 (1992-07-01), Sakashita et al.
patent: 5150366 (1992-09-01), Bardell, Jr. et al.
patent: 5181191 (1993-01-01), Farwell
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5381420 (1995-01-01), Henry
patent: 5392296 (1995-02-01), Suzuki
patent: 5426650 (1995-06-01), Ganapathy et al.
patent: 5428622 (1995-06-01), Kuban et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5448575 (1995-09-01), Hashizume
patent: 5448576 (1995-09-01), Russell
patent: 5872908 (1999-02-01), Whetsel
patent: 5991908 (1999-11-01), Baxter et al.
Unknown, "IEEE Standard Test Access Port and Boundary-Scan Architecture", Aug. 17, 1990, IEEE Std 1149.1-1990, Inst. of Electrical and Electronics Engineers, Inc., NY.
V.Agrawal, C. Kime and K. Saluja, "A Tutorial on Built-In Self-Test", Jun. 1993, pp. 69-77, Univ. of Wisconsin, Madison.
G.M. Blair, "Skew-free clock distribution for standard-cell VLSI designs," Apr. 1992, vol. 139, No. 2, pp. 211-213, Institution of Electrical Engineers, NY.
H. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI", 1990, pp. 367-385, Addison-Wesley VLSI System Series.
P. Varma, "On Path Delay Testing in a Standard Scan Environment", 1994 IEEE, CrossCheck Technology, Inc., San Jose, CA.
Adaptec, Inc.
Chung Phung M.
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