Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-05
2008-11-04
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000, C714S724000, C714S736000, C714S742000, C714S824000, C714S025000, C714S032000, C714S715000, C703S014000, C703S015000, C702S119000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07447966
ABSTRACT:
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.
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Michael Orr et al., Script/Simulation Approach Speeds SoC Verification, EE Times, Feb. 5, 2002.
Bass Bradley Forrest
Gens Erich Matthew
Hoda Sahir Shiraz
Kamannavar Anand V.
Zelle Nathan Dirk
Hewlett-Packard Development Company
Trimmings John P
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