Hierarchical built-in self-test for system-on-chip design

Details Hierarchical built-in self-test for system-on-chip design Hierarchical built-in self-test for system-on-chip design

2001-05-23

2004-04-27

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

06728916

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to built-in-self-test design in and for computer chips.
BACKGROUND OF THE INVENTION
Built-in self-test (BIST) design has been commonly implemented in memory and microprocessor chips. Some BIST designs are used only once during wafer-level or module-level testing to screen out bad chips. Other BIST designs are used to conduct self-checking and repairing after each power-on, throughout the lifetime of the chip. In today's high-density, high-performance chip design, BIST has become a critical circuit component that determines the product's development cost and time to market.
A typical BIST circuit in a high-density dynamic random access memory (DRAM) includes a controller, cache, pattern generator, and data comparator. (For instance, see Jeffery Dreibelbis, et al, “Processor-Based Built-In Self-Test for Embedded DRAM”, IEEE Journal of Solid State Circuits, Vol. 33, No. 11, November 1988, pp. 1731-1739.) The controller uses signal bits to communicate with an external tester. Different test modes such as START, STOP, CONTINUE, REFRESH, READ, and WRITE can be carried out by programming the signal bits. Typically, the cache can store 256 20-bit instruction words in multiple programs. After the chip is powered on, the cache will be loaded with a set of test programs, which determines how the DRAM will be tested. The pattern generator is capable of generating common test patterns such as solid ‘1’, solid ‘0’, checkerboard, row stripe, column stripe, and march pattern. The data comparator compares the data read from DRAM with the expected data that are written to DRAM, and determines whether the circuit passes or fails the test.
A more detailed analysis can be performed during wafer burn-in or module burn-in. After scanning each row and column of the DRAM array, a built-in address stack register array will store the addresses with the highest fail counts. These addresses will be used for repairing by activating redundancies via fuse programming techniques.
By placing many different macros on a single chip, a system-on-chip (SOC) design takes full advantage of the integration technique to achieve multi-function operations. For example, a wireless communication chip may comprise an embedded DRAM memory macro, a Flash memory macro, a microprocessor core, a mixed signal macro, and some analog macros. One of the challenges of designing a complicated system chip is to verify its design. However, since most input and output pins of each macro become inaccessible after integration, it is difficult to conduct a reliable high-speed and low-cost testing of a system chip.
Since most existing built-in self-test circuits are tailored to the individual macros, the BIST design for single memory or processor chips cannot be applied to the system chip that includes both the memory and processor macros. The BIST design for memory testing cannot be used directly for processor testing, and vice versa. In addition, there is no known BIST design for analog, radio frequency (RF), and mixed signal macros. The lack of communication and coordination among the tests of different macros will further compound the complexity of the problem.
Accordingly, a need has been recognized in connection with providing an effective built-in self-test methodology to conduct the complete system-on-chip testing, to ensure the circuit reliability and performance of system-on-chip design.
SUMMARY OF THE INVENTION
In accordance with at least one presently preferred embodiment of the present invention, a hierarchical built-in self-test (BIST) design method is provided for testing an integrated system chip with various functional blocks and macros.
The present invention also broadly contemplates, in accordance with at least one embodiment, the provision of a central BIST controller, one or more local BIST circuits for each macro, and data/control paths to perform the system on chip (SOC) test operations.
Further contemplated herein is the provision of a hierarchical test methodology that allows various levels (or more than one level) of testing on different macros. For example, the highest level of testing detects each macro's faults that are not reparable. The next level of testing detects the macro interface's faults that are not reparable. The following levels of testing may include self-repairing, self-tuning, and parameter adjustment for each macro to ensure its performance and functionality. The last level of testing conducts interface debugging and yield analysis, and sends reports to the external tester.
In accordance with at least one presently preferred embodiment of the present invention, a central BIST controller comprises: programmable devices for storing the test patterns and programming the test commands for each macro; a state machine for executing the test sequence for each macro in an orderly manner; a dynamic random access memory (DRAM) for collecting the feedback data from the local BIST circuits; and a built-in processor for conducting intra-macro and inter-macro testing via programs from an external tester.
Additionally contemplated herein is the provision of a test algorithm that performs self-testing and sets stopping criteria in a hierarchical and parallel manner to reduce the total test time.
In summary, one aspect of the invention provides an apparatus for providing hierarchical built-in self-testing for a system-on-chip, the apparatus comprising: a central BIST controller; at least one local BIST circuit; and at least one communication medium provided between the central BIST controller and the at least one local BIST circuit.
Another aspect of the invention provides a method of providing hierarchical built-in self-testing for a system-on-chip, the method comprising the steps of: providing a central BIST controller; providing at least one local BIST circuit; and communicating between the central BIST controller and the at least one local BIST circuit.
Furthermore, another aspect of the invention provides a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for providing hierarchical built-in self-testing for a system-on-chip, the method comprising the steps of: providing a central BIST controller; providing at least one local BIST circuit; and communicating between the central BIST controller and the at least one local BIST circuit.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.


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J. Dreibelbis et al., “Processor-Based Built-In Self-Test for Embedded DRAM”, IEEE Journal of Solid State Circuits, vol. 33, No. 11, Nov. 1998, pp. 1731-1739.

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