High speed built-in self-test circuit for DRAMS

Details High speed built-in self-test circuit for DRAMS High speed built-in self-test circuit for DRAMS

1999-04-12

2002-02-26

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S724000

Reexamination Certificate

active

06351837

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the testing of dynamic random access memory (DRAM). More specifically, this invention relates to a built-in self-test circuit for DRAM using two finite state machines.
BACKGROUND OF THE INVENTION
One objective of built-in self-test (BIST) for random access memory (RAM) is to translate a test algorithm into a sequence of commands, data, and addresses applied to the memory under test. In the prior art, a variety of techniques have been utilized to provide BIST for RAM. Traditionally, a hard-wired finite state machine is used to implement the translation process. To provide the capability of at-speed testing, the BIST circuit must operate as fast as the memory under test. A disadvantage of this approach is that the finite state machine is tailored to a specific set of test patterns whose complexity depends on the test algorithm. As the complexity of the test algorithm increases, this approach may be inadequate because the finite state machine may become too large and too slow to produce a test pattern in each clock cycle to intensively exercise the memory under test.
Other BIST circuits, known to be programmable or configurable, provide a certain amount of flexibility by configuration variables that determine the specific test pattern and sequence to be applied to the memory array. For example, U.S. Pat. No. 5,173,906 entitled “Built-in Self Test for Integrated Circuits” (issued Dec. 22, 1992 to Dreibelbis et al.) discloses a circuit that provides both fixed and programmable test patterns for a RAM array. U.S. Pat. No. 5,224,101 entitled “Micro-Coded Self-Test Apparatus for a Memory Array” (issued Jun. 29, 1993 to Popyack, Jr.) discloses a circuit that uses a micro-coded sequence defined in a read-only memory to produce the test patterns. U.S. Pat. No. 5,301,156 entitled “Configurable Self-Test for Embedded RAMs” (issued Apr. 5, 1994 to Talley) discloses a circuit that has a serial path that passes through the address, command, and data portions of the circuit to shift in a test or control pattern and to shift out the results, each scan requiring several clock cycles.
Each of these prior art techniques exhibits one or more drawbacks. Therefore, what is needed is a BIST circuit that is simple to implement and can handle high speeds.
SUMMARY OF THE INVENTION
A built-in self-test (BIST) circuit for a DRAM is disclosed. The BIST circuit comprises: a producer for producing a sequence of macro-instructions corresponding to a sequence of test patterns for input to said DRAM, said sequence of macro-instructions for implementing an underlying test algorithm; a scheduler for processing each individual macro-instruction in said sequence of macro-instructions into a sequence of one-hot encoded test patterns, each one-hot encoded test pattern including a memory command portion; a first-in first-out queue for synchronizing the provision of macro-instructions to said scheduler from said producer; an encoder for mapping said memory command portion of said one-hot encoded test pattern generated by said scheduler to a code defined by the DRAM; an output buffer for serving as a buffer between the BIST circuit and the DRAM; a delay buffer for delaying an expected memory response; and a comparator for comparing an output responses of the DRAM with the expected memory response from said delay buffer to determine if the function of the DRAM is correct.


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