Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-11-29
2004-06-15
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06751768
ABSTRACT:
BACKGROUND
The present invention concerns testing of integrated circuits and pertains particularly to hierarchical creation of vectors for quiescent current tests for system-on-chip circuits.
Integrated circuits are extensively tested by a manufacturer to assure correction functioning and reliability. Quiescent current (IDDQ) tests check for short circuits and other processing faults by loading test vectors into the circuit and monitoring current loads. Abnormal or unexpected current loads can indicate processing faults within the circuit.
Generally, to perform an IDDQ test, a series of test flip-flops located throughout the circuit are loaded with a test vector before each test. A test vector may include hundreds or even thousands of bits, depending upon the complexity of the circuit to be tested. While it would be desirable to perform an exhaustive test of the circuit using every possible test vector value, the test vector size and the time required to test the circuit using each test vector make such testing impractical. Therefore, it is important to generate a set of test vectors that will efficiently test the circuit and have a high probability of detecting any faults.
Software programs are typically used to generate test vectors for IDDQ tests. The software programs receive as input a file describing the circuitry of the circuit and produce a set of test vectors that will test the circuit. However, as circuits increase in complexity and the number of components within a circuit increases, the processing power and time required to generate test vectors increases. It is desirable, therefore, to develop more efficient ways to generate test vectors.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.
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Jaarsma Neal C.
Muradali Fidel
O'Brien Garrett
Sul Chinsong
Agilent Technologie,s Inc.
Ton David
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